System and method for reducing latency in a memory array decoder circuit

ABSTRACT

A system and method are disclosed for reducing latency in asserting a word-line for read/write operations of a memory row in a memory array. One embodiment of the present invention includes a memory array decoder circuit. The memory array decoder comprises a level-shifting NAND-gate operative to receive a plurality of pre-decode inputs having a first voltage range. The level-shifting NAND-gate is further operative to generate a level-shifted NAND output signal that is a NAND output of the plurality of pre-decode inputs and has a second voltage range that is greater than the first voltage range. The memory array decoder circuit also comprises an output inverter operative to invert the level-shifted NAND output signal to generate a decode signal.

TECHNICAL FIELD

This invention relates to electronic circuits, and more specifically to a system and method for reducing latency in a memory array decoder circuit.

BACKGROUND

Many types of random access memory (RAM) circuits use transistor driven data cells to latch bits of data for memory storage and are used in a large variety of consumer electronics, such as computers and cellular telephones. Data cells in a RAM circuit are typically arranged in an array, such that the RAM includes individually addressable rows and columns to which data can be written and from which data can be read. The individually addressable rows and columns are controlled by peripheral circuitry that receives decoded signals corresponding to memory locations, which could be generated from a processor, such that the peripheral circuitry determines which of the data cells in the array are written to or read from at any given time.

The market for consumer electronics, however, is constantly improving. There is an increasing demand to add more functionality and improve performance of current products while consuming less power for the purpose of conserving battery-life, such as in wireless communication applications. A given memory array of a RAM may require a higher operating voltage for read/write operations, but such a higher voltage potential may not be needed by associated peripheral circuitry to address the memory array for the read/write operations during less performance intensive memory operations. Therefore, one attempt to achieve lower power consumption is to reduce the operating voltage of the peripheral circuitry relative to the read/write voltage of memory cells in the memory array for less performance intensive memory operations. A level-shifter circuit is commonly used for this dual voltage-supply memory array system, such that the voltage potential of the peripheral circuitry can be reduced relative to the read/write voltage of the memory cells in the memory array to achieve lower power consumption while maintaining operational integrity of the memory circuit.

FIG. 1 illustrates a prior art example of a memory peripheral circuit 10. The memory peripheral circuit 10 includes a pre-decoder circuit 12. The pre-decoder circuit 12 receives inputs (not shown) from, for example, a processor to generate a three-bit decoding system for activating a given word-line, for example, to address a memory row of a memory array. In the example of FIG. 1, the pre-decoder 12 generates a pre-decode signal PRE_A, a pre-decode signal PRE_B, and a pre-decode signal PRE_C, each at a voltage V_(DDL) when logic-high. The three pre-decode signals PRE_A, PRE_B, and PRE_C are each input to a decoder circuit 14. The decoder circuit 14 includes a NAND-gate 16, a level-shifter 18, and an inverter 20. The NAND-gate 16 receives the three pre-decode signals PRE_A, PRE_B, and PRE_C and generates a decode signal at a node 22 that is input to the level-shifter 18. As described above, each of the three pre-decode signals PRE_A, PRE_B, and PRE_C are at a voltage V_(DDL) when logic-high, which could be an operating voltage that is less than an operating voltage required for read/write operations to an associated memory array (not shown), such that power consumption can be reduced. Accordingly, the level-shifter 18 can increase the voltage potential of the decode signal and output a level-shifted decode signal at a node 24, the level-shifted decode signal having a logic-high voltage V_(DDH) that is greater than the voltage V_(DDL). The level-shifted decode signal is then inverted by the inverter 20 to generate a decode signal WL at a node 26. The decode signal WL, having a voltage V_(DDH) when logic-high, activates a word-line to address a memory row of the associated memory array for read/write operations.

As described above, the example of FIG. 1 results in reduced power consumption as the peripheral circuitry operates at a lower voltage potential than the voltage necessary for read/write operations. However, the addition of logic gates and transistor switches to a given circuit introduces additional latency in activating a word-line to perform the read/write operations of a memory row. Accordingly, the reduction of power consumption of the memory peripheral circuit 10 of FIG. 1 sacrifices performance, as the addition of the level-shifter 18 increases latency in the decoding of the three pre-decode signals PRE_A, PRE_B, and PRE_C to assert the decode signal WL.

To demonstrate the latency stages of the memory peripheral circuit 10 of FIG. 1, it is to be understood that a latency stage can be latency resulting from the activation of a transistor by biasing a gate terminal. For example, the NAND-gate 16 can result in a single latency stage at the node 22 because a typical NAND-gate generates an output from the approximately simultaneous activation of one or more transistors. The level-shifter 18 can result in two latency stages at the node 24, as may be characteristic of the sequential activation of two transistors of a typical level-shifter. Additionally, the inverter 20 can result in a latency stage at the node 26 because a typical inverter generates an output from the activation of one of two transistors. Therefore, the assertion of the decode signal WL at the node 26 may have undergone four total stages of latency through the decoder circuit 14. Accordingly, the reduction of power consumption in the memory peripheral circuit 10 may result in a decrease in operating performance of the RAM associated with a given memory system.

SUMMARY

One embodiment of the present invention includes a memory array decoder circuit. The memory array decoder comprises a level-shifting NAND-gate operative to receive a plurality of pre-decode inputs having a first voltage range. The level-shifting NAND-gate is. further operative to generate a level-shifted NAND output signal that is a NAND output of the plurality of pre-decode inputs and has a second voltage range that is greater than the first voltage range. The memory array decoder circuit also comprises an output inverter operative to invert the level-shifted NAND output signal to generate a decode signal.

Another embodiment of the present invention includes a personal electronic device (PED). The PED comprises power source operative to provide power to the PED and a processor operative to generate a plurality of address signals. The PED also comprises a memory array that comprises a plurality of word-lines associated with respective memory rows of the memory array. The PED also comprises peripheral circuitry operative to receive the plurality of address signals and output a plurality of sets of pre-decode signals having a first voltage range. The PED also comprises a plurality of level-shifting NAND-gates operative to receive a respective set of pre-decode signals and to generate a level-shifted NAND output signal that is a NAND output of the set of pre-decode signals and has a second voltage range. The second voltage range can be greater than the first voltage range. The level-shifting NAND output signal is operative to activate a given one of the plurality of word-lines for read/write operations of the respective memory row based on a logic state of the respective set of pre-decode signals.

Another embodiment of the present invention includes a memory array decoder circuit. The memory array decoder circuit comprises means for generating a plurality of pre-decode signals having a first voltage range. The memory array decoder circuit also comprises means for concurrently performing a logical NAND operation and level-shifting the plurality of pre-decode signals to generate a level-shifted NAND output signal for activating a word-line associated with the memory array circuit. The level-shifted NAND output signal has a second voltage range, the second voltage range being greater than the first voltage range.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a prior art example of a memory peripheral circuit.

FIG. 2 illustrates an example of a memory peripheral circuit in accordance with an aspect of the invention.

FIG. 3 illustrates an example of a memory array decoder circuit in accordance with an aspect of the invention.

FIG. 4 illustrates an example of a timing diagram of the memory array decoder circuit of FIG. 3 in accordance with an aspect of the invention.

FIG. 5 illustrates a personal electronic device including a memory array decoder circuit in accordance with an aspect of the invention.

DETAILED DESCRIPTION

The present invention relates to electronic circuits, and more specifically to a system and method for reducing latency in a memory array decoder circuit. Power consumption can be reduced in a RAM without sacrificing performance by operating the RAM peripheral circuitry at a reduced voltage relative to the read/write voltage and by decreasing the number of latency stages of the decoder circuit. Level-shifting circuitry can be integrated into the NAND-gate circuitry in the decoder circuit, such that the resultant output signal for activating a word-line associated with a memory row of the memory array can be activated at an increased voltage with a reduced number of latency stages. Pre-decode signals input to the level-shifting NAND-gate can have a lower voltage potential than could be necessary for read/write operations of a memory array. A level-shifted NAND output signal can be set logic-low through a single latency stage. The voltage potential of the level-shifted NAND output signal can be greater than the lower voltage potential of the pre-decode signals. The level-shifted NAND output signal can then be inverted to generate a decode signal for activating a word-line of a memory array.

FIG. 2 illustrates an example of a memory peripheral circuit 50 in accordance with an aspect of the invention. The memory peripheral circuit 50 includes a pre-decoder circuit 52. The pre-decoder circuit 52 receives address inputs (not shown) from, for example, a processor to generate a three-bit decoding system for activating a given word-line, for example, to address a memory row of a memory array. In the example of FIG. 2, the pre-decoder 52 generates a pre-decode signal PRE_A, a pre-decode signal PRE_B, and a pre-decode signal PRE_C, each at a voltage V_(DDL) when logic-high. The three pre-decode signals PRE_A, PRE_B, and PRE_C are each input to a decoder circuit 54. The decoder circuit 54 includes a level-shifting NAND-gate 56 and an inverter 58. The level-shifting NAND-gate 56 receives the three pre-decode signals PRE_A, PRE_B, and PRE_C and generates a level-shifted NAND output signal LSNO at a node 60.

As described above, each of the three pre-decode signals PRE_A, PRE_B, and PRE_C operate at a voltage range between ground and a voltage potential V_(DDL). The voltage potential V_(DDL) could be an operating voltage that is less than an operating voltage required for read/write operations to an associated memory array (not shown), such that power consumption can be reduced. Accordingly, the level-shifting NAND-gate 56 includes integral level-shifting circuitry that can increase the voltage potential of the decode signal to from the voltage potential V_(DDL) a voltage VDDH when logic-high, such that the level-shifted NAND output signal LSNO operates at a voltage range between ground and the voltage potential V_(DDH). The voltage V_(DDH) can be greater than the voltage V_(DDL), such that the voltage V_(DDH) can be sufficient to activate a word-line for read/write operations of the associated memory array. The level-shifted NAND output signal LSNO is then inverted by the inverter 58 to generate a decode signal WL at a node 62. The decode signal WL, having a voltage V_(DDH) when logic-high, activates a word-line of the associated memory array for read/write operations.

The level-shifting circuitry that is integral to the level-shifting NAND-gate 56 does not increase the latency involved in performing the NAND-operation on the three pre-decode signals PRE_A, PRE_B, and PRE_C when asserting the decode signal WL. Therefore, by including the level-shifting circuitry integral to the level-shifting NAND-gate 56, the level-shifted decode signal WL can be asserted based on the three pre-decode signals PRE_A, PRE_B, and PRE_C of a lower voltage potential with reduced latency. To demonstrate the latency stages of the memory peripheral circuit 50 of FIG. 2, the level-shifting NAND-gate 56 results in a single latency stage at the node 60. Additionally, the inverter 58 results in a single latency stage at the node 62. Therefore, the assertion of the decode signal WL to a logic-high state at the node 62 may have undergone only two total stages of latency through the decoder circuit 54. Thus, the level-shifting NAND-gate 56 concurrently provides a logical NAND operation and level-shifting of the three pre-decode inputs PRE_A, PRE_B, and PRE_C. Accordingly, the memory peripheral circuit 50 in the example of FIG. 2 can activate a word-line for read/write operations at reduced power consumption while maintaining operating performance of the associated RAM by reducing latency.

It is to be understood that the memory peripheral circuit 50 in the example of FIG. 2 is but one example of a memory peripheral circuit implementation. As such, in accordance with an aspect of the invention, other designs can be realized. For example, the memory peripheral circuit 50 is not limited to a three-bit decoding system, but could include two, or more than three, separate pre-decoded signals. Additionally, the peripheral circuitry voltage V_(DDL) need not be fixed, but could instead be variable, such that the memory read/write voltage V_(DDH) could be greater than or equal to the peripheral circuitry voltage V_(DDL).

FIG. 3 illustrates an example of a memory array decoder circuit 100 that includes a level-shifting NAND-gate 102 in accordance with an aspect of the invention. The level-shifting NAND-gate receives a pre-decode input PRE_A, a pre-decode input PRE_B, and a pre-decode input PRE_C as inputs. It is to be understood that the example of FIG. 3 is not limited to three pre-decode inputs, but could instead include two, or more than three, separate pre-decode inputs. Each of the three pre-decode inputs PRE_A, PRE_B, and PRE_C could be generated by a pre-decoder and could have a voltage range between V_(DDL) when logic-high and a negative voltage supply V_(SS), which could be ground, when logic-low.

The pre-decode inputs PRE_B and PRE_C are input to an internal NAND-gate 104 which generates a NAND output signal NAND_O. In the above example of more or less than three pre-decode inputs, the internal NAND-gate 104 could receive a proper subset (i.e., less than all) of the pre-decode inputs. As described above, the pre-decode inputs have a voltage range between V_(DDL) when logic-high and a negative voltage supply V_(SS) , and thus the internal NAND-gate 104 is referenced to the voltage V_(DDL). The level-shifting NAND-gate 102 also includes an N-type field effect transistor (FET) N1. The N-FET N1 interconnects a node 106 to the NAND output signal NAND_O, and has a gate terminal that is coupled to the pre-decode input PRE_A. The node 106 is the node that generates a level-shifted NAND output signal LSNO, such as the level-shifted NAND output signal LSNO at the node 60 in the example of FIG. 2. Accordingly, upon the three pre-decode inputs PRE_A, PRE_B, and PRE_C being logic-high, the NAND output signal NAND_O is logic-low, and the pre-decode input PRE_A activates the N-FET N1. Accordingly, the node 106 becomes coupled to the logic-low state of the NAND output signal NAND_O, thus resulting in the level-shifted NAND output signal LSNO being switched to logic-low. As will be described in more detail below, the N-FET NI may be a larger transistor, capable of greater current flow than other transistors in the memory array decoder circuit 100.

The level-shifting NAND-gate 102 also includes a switching stage 108. The switching stage 108 includes a P-type FET P1 and two N-type FETs N2 and N3. The NAND output signal NAND_O is coupled to a gate terminal of the P-FET P1 and the N-FET N2. The pre-decode input PRE_A is input to an inverter 110, which is referenced to the voltage V_(DDL) and generates a signal PRE_A′. The signal PRE_A′ is coupled to a gate terminal of the N-FET N3. The P-FET P1 interconnects the pre-decode input PRE_A and a control node 112. The N-FETs N2 and N3 each interconnect the control node 112 and the negative voltage supply V_(SS) . The control node 112 is also coupled to an N-type FET N4 and a P-type FET P2. The N-FET N4 interconnects the node 106 and the negative voltage supply V_(SS) . The P-FET P2 is an activation FET for a level-shifter sub-circuit 114. The level-shifter sub-circuit 114 couples the node 106 to a positive voltage supply V_(DDH), as is explained in more detail below. The positive voltage supply V_(DDH) can be equal to or greater than the pre-decode input voltage V_(DDL). Accordingly, the control node 112 controls a logic state of the node 106 to switch the level-shifted NAND output signal LSNO between a voltage range of V_(DDH) at logic-high and V_(SS) at logic-low.

As an example, when the control node 112 is logic-high, the P-FET P2 is deactivated, thus decoupling the node 106 from the positive voltage supply V_(DDH). However, the N-FET N4 activates, thus coupling the node 106 to the negative voltage supply V_(SS) . It is to be understood that the switching of the N-FET N4 is therefore redundant, as the node 106 will have already been coupled to the logic-low NAND output signal NAND_O via the N-FET N1. The N-FET N4 is thus included to enhance the circuit operation at the reduced pre-decode input voltage V_(DDL) by providing a more robust switching of the node 106. When the control node 112 is logic-low, the N-FET N4 is deactivated, thus decoupling the node 106 from the negative voltage supply V_(SS) . However, the P-FET P2 activates, thus coupling the node 106 to the positive. voltage supply V_(DDH) via the level-shifter sub-circuit 114. Therefore, the level-shifted NAND output signal LSNO becomes logic-high. The level-shifted NAND output signal LSNO is input to an inverter 116 to generate a decode signal WL having a voltage substantially equal to V_(DDH) at logic-high and substantially equal to V_(SS) at logic-low. The decode signal WL is operative to activate a word-line of an associated memory array for read/write operations.

The level-shifter sub-circuit 114 includes additional P-type FETs P3, P4, and P5. An N-type FET N5 and an N-type FET N6 work in conjunction with the inverter 110 to activate and deactivate the level-shifter sub-circuit 114. As an example, the N-FETs N5 and N6 are coupled to the signal PRE_A′ and the NAND output signal NAND_O, respectively. If any of the three pre-decode inputs PRE_A, PRE_B, and PRE_C are logic-low, at least one of the N-FETs N5 and N6 will activate and couple a node 118 to the negative voltage supply V_(SS) , thus activating the P-FET P3. Any combination of inputs from the three pre-decode inputs PRE_A, PRE_B, and PRE_C that results in either of the N-FETs N5 and N6 being activated would also have activated either of the N-FETs N2 and N3, as well, thus also activating the P-FET P2, and in turn deactivating the P-FET P4. Accordingly, the node 106 becomes coupled to the positive voltage supply V_(DDH), and the level-shifted NAND output signal LSNO becomes logic-high. As described above, in the event that all three of the pre-decode inputs PRE_A, PRE_B, and PRE_C are logic-high, both the N-FETs N5 and N6 will have deactivated and the N-FET N1 will have activated, thus setting the node 106 logic-low. Accordingly, the P-FET P2 becomes deactivated, decoupling the node 106 from the positive voltage supply V_(DDH). Therefore, the combination of the N-FETs N1-N6 and the P-FETs P1-P5 comprise the level-shifting NAND-gate 102, such that the level-shifted NAND output signal LSNO at the node 106 is a NAND output for the three pre-decode inputs PRE_A, PRE_B, and PRE_C.

The memory array decoder circuit 100 is capable of providing not only level-shifting of the three pre-decode inputs PRE_A, PRE_B, and PRE_C from a peripheral circuitry voltage to a higher memory read/write voltage for reduced power consumption, but is also able to assert the decode signal WL with a reduced latency to maintain performance. FIG. 4 demonstrates an example of a timing diagram associated with the memory array decoder circuit 100 in accordance with an aspect of the invention. In the example of FIG. 4, the three pre-decode inputs PRE_A, PRE_B, and PRE_C are asserted (i.e., logic 1) at a time T0, and de-asserted (i.e., logic 0) at a time T6. Subsequent to the time T0, FIG. 4 demonstrates five separate times T1, T2, T3, T4, and T5 that each represent latency stages associated with the assertion of the three pre-decode inputs PRE_A, PRE_B, and PRE_C. For example, the time T1 corresponds to a single latency stage, the time T2 corresponds to two latency stages, etc. In addition, the example of FIG. 4 also demonstrates seven separates times T7, T8, T9, T10, T11, T12, and T13 corresponding to latency stages associated with the de-assertion of the three pre-decode inputs PRE_A, PRE_B, and PRE_C. At a time T14, the three pre-decode inputs PRE_A, PRE_B, and PRE_C become asserted again. In the example of FIG. 4, is demonstrated as an ideal timing diagram, such that the illustrated rising-edges and falling-edges of the associated signals are instantaneous. However, it is to be understood that there will be inherent timing delays in the assertion and de-assertion of the signals demonstrated in the example of FIG. 4. In addition, the latency times T1-T5 and T7-T13 are all demonstrated as having a substantially equal duration. However, it is to be further understood that the latency times could all have varying durations of time depending on the switching times of the associated transistors.

Referring to the examples of FIGS. 3 and 4, the decode signal WL is asserted after only two stages of latency, as opposed to the four stages of latency illustrated in the prior art example of FIG. 1. As described above, a typical NAND-gate generates an output from the approximately simultaneous activation of one or more transistors. Accordingly, the internal NAND-gate 104 results in a single latency stage in the generation of the NAND output signal NAND_O from the pre-decode inputs PRE_B and PRE_C, as demonstrated at the time T1. Additionally, the activation of the N-FET N1 via the pre-decode input PRE_A results in a single latency stage, coupling the NAND output signal NAND_O to the node 106. Accordingly, because the pre-decode input PRE_A is not input to the internal NAND-gate 104, the activation of the N-FET N1 and the internal NAND-gate 104 is not sequential, and is thus approximately simultaneous. Therefore, upon asserting the three pre-decode inputs PRE_A, PRE_B, and PRE_C to a logic-high state, the signal LSNO at the node 106 switches to a logic-low state after only a single stage of latency, as demonstrated at the time T1. The inverter 116 results in an additional stage of latency because a typical inverter generates an output from the activation of one of two transistors. Therefore, as demonstrated at the time T2, the memory array decoder circuit 100 results in two stages of latency in asserting the decode signal WL to activate a word-line for read/write operations. Accordingly, the level-shifting NAND-gate 102 concurrently provides a logical NAND operation and level-shifting of the three pre-decode inputs PRE_A, PRE_B, and PRE_C.

In addition, as described above, the N-FET N4 provides a more robust switching of the node 106, and the N-FETs N5 and N6 deactivate the level-shifter sub-circuit 114. At the time T1, the signals NAND_O and PRE_A′ are de-asserted as a result of the single latency stage of the internal NAND-gate 104 and the inverter 110, respectively. Therefore, the N-FETs N5 and N6 are deactivated, allowing the node 118 to be switched to a logic-high state after two latency stages at the time T2 due to the activation of the P-FETs P4 and P5. In addition, the logic-low state of the NAND output signal NAND_O activates the P-FET P1, coupling the node 112 to the pre-decode signal PRE_A. Therefore, the node 112 also becomes switched to a logic-high state after two latency stages at the time T2. Upon the node 112 being switched logic-high, the N-FET N4 activates to couple the node 106 to the negative voltage supply V_(SS) . Accordingly, after three latency stages at the time T3, the level-shifted NAND output signal LSNO at the node 106 becomes coupled to the negative voltage supply V_(SS) , thus providing the redundancy described above.

Referring back to FIG. 3, the level-shifting NAND-gate 102 also includes an output reset stage 120. The output reset stage 120 includes a P-type FET P6, a P-type FET P7, and three inverters 122. The P-FETs P6 and P7 are series interconnected between the positive voltage supply V_(DDH) and the node 106. The three inverters 122 are series interconnected between the decode signal WL and a gate terminal of the P-FET P6, the gate terminal of the P-FET P6 being coupled to a node 124. The P-FET P7 has a gate terminal that is coupled to the node 118. Further to the above discussion with reference to FIG. 4, upon the three pre-decode signals PRE_A, PRE_B, and PRE_C being asserted at the time T0, the node 124 becomes logic-low five latency stages later at the time T5. It is to be understood that the output reset stage 120 is not limited by the example of FIG. 3. For example, the output reset stage 120 could include more or less odd numbers of inverters 122. The output reset stage 120 operates to provide rapid transitions of the decode signal WL by overcoming parasitic capacitance created by other devices in the circuit, such as the inverter 116, and by preventing conflicting pull-up and pull-down conditions.

As an example, upon the three pre-decode signals PRE_A, PRE_B, and PRE_C being de-asserted at the time T6, the control node 112 and the node 118 each transition from logic-high to logic-low in about two stages of latency, as demonstrated at the time T8. Therefore, the logic-low state of the control node 112 deactivates the N-FET N4 and activates the P-FET P2. Concurrently, the logic-low state of the node 118 activates P-FET P3. Thus, the level-shifted NAND output signal LSNO at the node 106 transitions from logic-low to logic-high at about three stages of latency at the time T9. Therefore, the level-shifted NAND output signal LSNO is inverted by the inverter 116, and the decode signal WL is switched logic-low at about four stages of latency at the time T10.

The transition of the node 118 from logic-high to logic-low also activates the P-FET P7. While the decode signal WL maintains a logic-high state, the P-FET P6 is activated. Therefore, activation of the P-FET P7 causes the node 106 to transition from a logic-low to a logic-high state. Since the node 124 is approximately four stages of latency behind the node 106, due to the inverter 116 and the three inverters 122, the node 124 does not become activated until the time T13. Accordingly, the P-FET P6 is still activated during the transition of the node 118. Therefore, the node 106 is coupled to the positive voltage supply V_(DDH) through both the P-FETs P3 and P2 and the P-FETs P6 and P7. It is to be understood that the P-FETs P6 and P7 may be larger transistors capable of greater current flow, such that they are able to overcome pull-down effects created by parasitic capacitance and/or the partial deactivation of the N-FET N4. A short time after the decode signal WL transitions from logic-high to logic-low (e.g., three latency stages later), the P-FET P6 deactivates, and thus the node 106 remains coupled to the positive voltage supply V_(DDH) only through the P-FETs P3 and P2.

To illustrate the reverse example, while the decode signal WL maintains a logic-low state, the P-FET P6 is deactivated, as described above, but the P-FET P7 is activated. Prior to a low-to-high logic transition of the decode signal WL, the N-FET N1 activates to switch the level-shifted NAND output signal LSNO at the node 106 to a logic-low state after a single latency stage, at the time T1. Accordingly, the N-FET N1 may be a larger transistor, capable of greater current flow, such that it is able to overcome pull-up effects of the P-FETs P3 and P2. However, because the P-FET P6 had already decoupled the node 106 from the positive voltage supply V_(DDH), the N-FET N1 is capable of pulling the node 106 down to a logic-low state without conflicting with the pull-up effect of the P-FET P7. After an additional latency stage, at the time T2, the control node 112 transitions from logic-low to logic-high. Thus, the control node 112 activates the N-FET N4 and deactivates the P-FET P2, thus providing the pull-down redundancy of the level-shifted NAND output signal LSNO at the node 106 from logic-high to logic-low at about three stages of latency, as described above. At approximately the same time, the P-FET P7 deactivates. A short time after the decode signal WL transitions from logic-low to logic-high (e.g., three latency stages later), the P-FET P6 reactivates. Accordingly, the output reset stage 120 provides rapid transitions of the decode signal WL by overcoming parasitic capacitance created by other devices in the circuit and by preventing conflicting pull-up and pull-down conditions.

FIG. 5 illustrates a personal electronic device (PED) 150 in accordance with an aspect of the invention. The PED 150 could be, for example, a mobile telephone, a personal digital assistant (PDA), and/or a laptop computer. The PED 150 includes an input/output (I/O) block 152 that could include at least one input device and at least one output device. The I/O block 152 receives user inputs, such as voice and information data, and displays, transmits, or otherwise conveys output information to one or more users. The PED 150 also includes a controller 154 coupled to the I/O block 152, which could include one or more processors and associated circuitry. The controller 154 is also coupled to a memory circuit 156, which could be a random access memory (RAM) operative to store user input/output data or control data. Accordingly, the controller 154 can facilitate operation between the I/O block 152 and the memory circuit 156. The PED 150 also includes a power source 158, which could be a battery. Accordingly, conserving power consumption of the PED may be an important factor in the operation of the PED.

The memory circuit 156 includes one or more memory arrays 160. Each of the memory arrays 160 can include a peripheral circuit 162, a plurality of decode circuits 164, and a plurality of memory rows 166. Each of the plurality of decode circuits 164 is associated with a given one of the plurality of memory rows 166. The peripheral circuit 162 can receive instructions from the controller 154 for activating a given word-line associated with a respective one of the memory rows 166 for read/write operations. The peripheral circuit 162 outputs a set of pre-decode signals that correspond to a given one of the decode circuits 164 for activating the word-line of the associated memory row 166 for read/write operations.

The peripheral circuit 162 can operate at a voltage range between ground and a voltage potential V_(DDL) to conserve power, whereas the voltage potential V_(DDL) may not be a voltage potential sufficient to activate the word-line associated with the memory row 166 for read/write operations. In the example of FIG. 5, at least one of the decode circuits 164 can include a level-shifting NAND-gate 168, such as, for example, the level-shifting NAND-gate 56 in the example of FIG. 2 or the level-shifting NAND-gate 102 in the example of FIG. 3. The level-shifting NAND-gate 168, when combined with an inverter 170, can operate to perform the decoding operation of the pre-decode signals and level-shift the output to a voltage range between ground and a voltage potential V_(DDH), whereas the voltage potential V_(DDH) is greater than or equal to the voltage potential V_(DDL). Accordingly, a decode circuit 164 that includes a level-shifting NAND-gate 168 can activate the word-line associated with the memory row 166 for read/write operations with reduced latency while conserving power.

What have been described above are examples of the present invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the present invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present invention are possible. Accordingly, the present invention is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims. 

1. A memory array decoder circuit comprising: a level-shifting NAND-gate operative to receive a plurality of pre-decode inputs having a first voltage range, the level-shifting NAND-gate being further operative to generate a level-shifted NAND output signal that is a NAND output of the plurality of pre-decode inputs and having a second voltage range, the second voltage range being greater than the first voltage range; and an output inverter operative to invert the level-shifted NAND output signal to generate a decode signal.
 2. The decoder circuit of claim 1, wherein the level-shifting NAND-gate comprises an N-type FET having a gate terminal coupled to a first of the plurality of pre-decode inputs, the N-type FET being operative to set the level-shifted NAND output signal to a logic-low state upon the plurality of pre-decode inputs being logic-high.
 3. The decoder circuit of claim 2, wherein the level-shifting NAND-gate further comprises an internal NAND-gate operative to receive a proper subset of the plurality of pre-decode inputs, and wherein the N-type FET interconnects the level-shifted NAND output signal with an output of the internal NAND-gate.
 4. The decoder circuit of claim 1, further comprising a switching stage comprising a control node, the switching stage being operative to switch the level-shifted NAND output signal logic-high upon the control node being logic-low, and to switch the level-shifted NAND output signal logic-low upon the control node being logic-high.
 5. The decoder circuit of claim 4, wherein the switching stage further comprises an input P-type FET that is interconnected between a first of the plurality of pre-decode inputs and the control node, the input P-type FET being controlled by a proper subset of the plurality of pre-decode inputs.
 6. The decoder circuit of claim 4, wherein the switching stage further comprises a pull-down FET having a gate terminal coupled to the control node, the pull-down FET being operative to couple the level-shifted NAND output signal to a negative voltage supply upon the control node being logic-high.
 7. The decoder circuit of claim 4, wherein the switching stage further comprises a first input N-type FET and a second input N-type FET interconnected between the control node and a negative voltage supply, the first and the second N-type FETs being controlled by the plurality of pre-decode inputs.
 8. The decoder circuit of claim 7, wherein the control node is coupled to a gate terminal of a P-type FET of a level-shifter sub-circuit, the level-shifter sub-circuit being operative to couple the level-shifted NAND output signal to a logic-high voltage potential upon the control node being logic-low, the logic-high voltage potential being an upper-limit of the second voltage range.
 9. The decoder circuit of claim 1, wherein the level-shifting NAND-gate further comprises an output reset stage operative to provide a rapid logic transition of the level-shifted NAND output signal.
 10. The decoder circuit of claim 9, wherein the output reset stage comprises a first P-type FET and a second P-type FET that are series interconnected between an upper-limit voltage potential of the second voltage range and the level-shifted NAND output signal, the output reset stage further comprising an odd number of a plurality of series-connected inverters interconnected between the decode signal and a gate terminal of the second P-type FET.
 11. The decoder circuit of claim 10, wherein the output reset stage switches the first P-type FET a predetermined time period after activation of the second P-type FET, such that the first P-type FET and the second P-type FET are held at the same state for the short time prior to the second P-type FET switching.
 12. A personal electronic device (PED) comprising: a power source operative to provide power to the PED; a processor operative to generate a plurality of address signals; a memory array comprising a plurality of word-lines associated with respective memory rows of the memory array; peripheral circuitry operative to receive the address signals and output a plurality of sets of pre-decode signals having a first voltage range; and a plurality of level-shifting NAND-gates, each level-shifting NAND-gate being operative to receive a respective set of pre-decode signals and to generate a level-shifted NAND output signal that is a NAND output of the set of pre-decode signals and having a second voltage range, the second voltage range being greater than the first voltage range, the level-shifting NAND output signal being operative to activate a given one of the plurality of word-lines associated with a respective one of the memory rows based on a logic state of the respective set of pre-decode signals.
 13. The PED of claim 12, wherein each of the plurality of level-shifting NAND-gates comprises an N-type FET having a gate terminal coupled to a first of the set of pre-decode signals, the N-type FET being operative to set the level-shifted NAND output signal to a logic-low state upon the set of pre-decode signals being logic-high.
 14. The PED of claim 13, wherein each of the plurality of level-shifting NAND-gates further comprises an internal NAND-gate operative to receive a proper subset of the set of pre-decode signals, and wherein the N-type FET interconnects the level-shifted NAND output signal with an output of the internal NAND-gate.
 15. The PED of claim 12, wherein each of the plurality of level-shifting NAND-gates comprises a switching stage comprising a control node, the switching stage being operative to switch the level-shifted NAND output signal logic-high upon the control node being logic-low, and to switch the level-shifted NAND output signal logic-low upon the control node being logic-high.
 16. The PED of claim 15, wherein the switching stage further comprises a pull-down FET having a gate terminal coupled to the control node, the pull-down transistor being operative to couple the level-shifted NAND output signal to a negative voltage supply upon the control node being logic-high.
 17. The PED of claim 12, wherein each of the plurality of level-shifting NAND-gates comprises an output reset stage operative to provide a rapid logic transition of the level-shifted NAND output signal.
 18. A memory array circuit comprising: means for generating a plurality of pre-decode signals having a first voltage range; and means for concurrently performing a logical NAND operation and level-shifting the plurality of pre-decode signals to generate a level-shifted NAND output signal for activating a word-line associated with the memory array circuit, the level-shifted NAND output signal having a second voltage range, the second voltage range being greater than the first voltage range.
 19. The memory array circuit of claim 18, further comprising means for inverting the level-shifted NAND output signal to generate a decode signal for activating the word-line associated with the memory row of the memory array.
 20. The memory array circuit of claim 18, wherein the means for setting a logic state of the node comprises means for providing a rapid logic transition of the output signal. 